This invention relates generally to electrical power delivery, and more particularly to power delivery in a heterogeneous three-dimensional stacked apparatus.
In distributing electrical power to an apparatus with multiple layers, the supply voltage can suffer voltage variations and IR drops between the lower layer and upper layers, where the apparatus receives a supply voltage at the lower layer. Voltage variations are fluctuations in voltage, and IR drops are static and dynamic losses on resistive loads in a current path. The IR drops become even more prominent in tungsten-based through-silicon-via (TSV) technologies. IR drops through tungsten-based TSVs may be attributed to electrical conductivity characteristics of tungsten, as well as aspect ratio and metallization limitations. Number, area, and placement restrictions on TSVs can also increase the IR drops between the layers. Board-level controlled collapse chip connection (C4) pitch restrictions and finer pitched power/ground vias can limit the efficiency of power delivery to the stacked layers. Power loss during voltage conversion between layers also reduces the overall energy efficiency of the apparatus.
A heterogeneous three-dimensional (3-D) stacked apparatus with multiple layers has further design challenges for power distribution. Individual device layers of a heterogeneous 3-D stacked apparatus can have different requirements in terms of target supply voltage, voltage variations sensitivity, and the like, including different requirements per layer and for tiles of the same layer. Power and thermal requirements can limit the ability to integrate a variety of technologies, architectures, and/or functionality into a heterogeneous 3-D stacked apparatus.